Semiconductor with a nitrided silicon gate oxide and method

ABSTRACT

A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.

TECHNICAL FIELD OF THE INVENTION

[0001] This invention relates generally to the field of integratedcircuit fabrication, and more particularly to a semiconductor with anitrided silicon gate oxide and a method for forming same.

BACKGROUND OF THE INVENTION

[0002] Presently, there is a great demand for shrinking semiconductordevices to provide an increased density of devices on the semiconductorchip that are faster and consume less power. The scaling of devices inthe lateral dimension requires vertical scaling as well so as to achieveadequate device performance.

[0003] Gate stacks may comprise a gate oxide overlying a gatedielectric. The gate oxide may comprise silicon dioxide or, morerecently, a nitrided gate oxide. Traditionally, plasma-assistednitridation of silicon oxide to form nitrided gate oxide structures isachieved by creating a silicon dioxide layer on the surface of asubstrate and reacting the silicon dioxide layer with ionized nitrogengenerated by a plasma source.

SUMMARY OF THE INVENTION

[0004] A method of fabricating a transistor includes providing asemiconductor substrate having a surface and forming a nitride layeroutwardly of the surface of the substrate. The nitride layer is oxidizedto form a nitrided silicon oxide layer comprising an oxide layer beneaththe nitride layer. A high-K layer is deposited outwardly of the nitridelayer, and a conductive layer is formed outwardly of the high-K layer.The conductive layer, the high-K layer, and the nitrided silicon oxidelayer are etched and patterned to form a gate stack. Sidewall spacersare formed outwardly of the semiconductor substrate adjacent to the gatestack, and source/drain regions are formed in the semiconductorsubstrate adjacent to the sidewall spacers.

[0005] Technical advantages of the present invention include an improvedgate dielectric with low nitrogen incorporation in the substrate. Thelow nitrogen incorporation increases electron mobility and limitsvoltage shift. In addition, low nitrogen incorporation limits migrationof oxygen atoms into the substrate and thus increases the efficiency oftransistor components.

[0006] Certain embodiments may possess none, one, some, or all of thesetechnical features and advantages and/or additional technical featuresand advantages. Other technical advantages will be readily apparent toone skilled in the art from the following figures, description, andclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present invention andits advantages, reference is now made to the following description,taken in conjunction with the accompanying drawings, in which:

[0008] FIGS. 1A-G are a series of schematic cross-sectional diagramsillustrating a method of method of fabricating a transistor inaccordance with one embodiment of the present invention; and

[0009]FIG. 2 is a graph illustrating a profile of atomic percentage ofnitrogen in the gate stack in accordance with one embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

[0010] FIGS. 1A-1G are a series of schematic cross-sectional diagramsillustrating a method of fabricating a transistor in accordance with oneembodiment of the present invention. The method shown in FIGS. 1A-1G maybe used in both positive metal oxide semiconductor (PMOS) and negativemetal oxide semiconductor (NMOS) devices.

[0011] Referring to FIG. 1A, substrate 10 may comprise a siliconsubstrate or silicon epitaxial layer. However, other substrates mayalternatively be used. Substrate 10 will conventionally have alreadyundergone several processing steps. For example, formation of isolationstructures 12 may have been performed. An oxide layer 14 may have formedon the surface of the substrate due to exposure of the substrate to airor otherwise.

[0012] Referring to FIG. 1B, the substrate 10 is stripped withhydrofluoric acid (HF) 16 or otherwise treated or cleaned so as toremove oxide layer 14 and/or other impurities from the surface of thesubstrate.

[0013] Referring to FIG. 1C, nitride layer 18 is formed outwardly of thesurface of the substrate 10. In one embodiment, nitride layer 18 may beformed outwardly of the substrate by being formed on the substrate. Inanother embodiment, nitride layer 18 may be formed outwardly of thesubstrate by being formed on an intermediate layer. In a particularembodiment, the nitride layer 18 may be formed by subjecting the surfaceof the substrate 10 to plasma 17. The source of nitrogen for the plasma17 may be a nitrogen containing precursor such as N₂ or NH₃ or a mixturethereof with a suitable inert gas (He, Ar, etc.) or oxidizing gas (NO,N₂ O, O₂, etc.). The plasma is preferably a high density plasma. Theplasma may be generated by a helical-resonator source, anelectron-cyclotron resonance source, or an inductively coupled source.

[0014] During plasma nitridation, the substrate 10 may be unbiased, inwhich case the ionized substances are accelerated by the plasmapotential (on the order of 20 Volts) and then implanted into thesubstrate 10 surface. A bias can be applied to the substrate 10 tofurther accelerate the ions from the plasma and implant them deeper intothe surface. Either a direct current (DC) or radio frequency (RF) biasmay be applied to the substrate 10.

[0015] In a particular embodiment, the plasma nitridation process maycomprise the following process conditions: plasma density between 1×10¹⁰to 1×10¹² cm⁻³; nitrogen flow between 1-2000 sccm preferably 1-100sccm); pressures on the order of 1-300 mTorr (preferably 1-50 mTorr),temperature in the range of 77 K to 773 K; substrate bias in the rangeof 0 to 200 Volts; a temperature may be less than about 500° C.; and aduration in the range of 1 to 300 seconds. Nitride layer 18 may comprisea mixture of Si₃N₄ and SiO_(x)N₄. In a particular embodiment, thenitride layer 12 may have a thickness of about 10-12 Angstroms.

[0016] Referring to FIG. 1D, after the formation of nitride layer 18,oxide layer 20 is formed beneath nitride layer 18. In a particularembodiment, oxide layer 20 is formed beneath nitride layer 18 by thermaloxidation of the substrate 10 and nitride layer 18. Thermal oxidation ina particular embodiment may take place at a temperature of about600-1000° C. in an oxidizing ambient such as O₂, N₂O, NO, dilute steam,or another suitable oxidant. The oxide layer 20 may comprise SiO₂, butmay also comprise an amount of nitrogen in the form of SiO_(x)N₄ orother compounds. Nitride layer 18 may retard the oxidation, resulting incontrol over the thickness of the oxide layer 20. Together, nitridelayer 18 and oxide layer 20 form nitrided silicon oxide layer 22. Thethickness of the nitrided silicon oxide layer 22 may be optimized forusing the nitrided silicon oxide as a gate oxide. In a particularembodiment, oxide layer 20 may have a thickness of about 2-10 angstromsand nitrided silicon gate oxide layer 22 may have a thickness of about14-20 angstroms.

[0017] Referring to FIG. 1E, in a particular embodiment, a gatedielectric 24 comprising a material with a high dielectric constant, orwith “high-K,” is formed outwardly of nitride layer 18. High-K is usedherein to refer to a dielectric material having a dielectric constantgreater than about 7. In particular embodiments, materials having adielectric constant from 7 to 30 may be used. The high-K dielectriclayer may comprise an oxygen-containing material such as Ta₂O₅, BaTiO₃,TiO₂, CeO₂, or barium strontium titanate. The high-K dielectric layer 24may be formed by thermal or plasma-assisted processes, atomic layerepitaxy, or by any other suitable methods.

[0018] Referring to FIG. 1F, conductive layer 26 is formed outwardly ofhigh-K layer 24. Conductive layer 26 may comprise polysilicon, metal, oranother suitable gate material.

[0019] Referring to FIG. 1G, conductive layer 26, high-K dielectriclayer 24, and nitrided silicon oxide layer 22 are patterned and etchedto form gate stack 28 including gate (layer 26) and gate dielectrics(layers 22 and 24). Fabrication of transistor 40 may be completed byimplanting drain extension regions 36, depositing and etching adielectric to form sidewall spacers 30, and implanting source/drainregions 32.

[0020]FIG. 2 is a graph illustrating an example profile of atomicpercentage of nitrogen in nitride layer 18 and oxide layer 20 accordancewith one embodiment of the present invention. Substrate 10, nitridelayer 18, and oxide layer 20 are shown on FIG. 2 relative to depth. Theprofile of atomic percentage of nitrogen reflects the oxidation of thenitride layer 18 and substrate 10 as described in reference to FIG. 1D.

[0021] In the illustrated embodiment, the atomic percentage of nitrogenat the top of nitride layer 18 is about 9% (and this value ranges from6% to 12% in particular embodiments), and the percentage peaks at 15%within nitride layer 18 (the peak may range from 10% to 20% inparticular embodiments). The percentage decreases with depth withinoxide layer 20, reaching about 11% at the. boundary between substrate 10and oxide layer 20 (and this value ranges from 8% to 14% in particularembodiments). Although example values and ranges of atomic percentage ofnitrogen have been given, it should be understood that any appropriatevalues may be used in particular embodiments.

[0022] Although the present invention has been described with severalembodiments, a myriad of changes, variations, alterations,transformations, and modifications may be suggested to one skilled inthe art, and it is intended that the present invention encompass suchchanges, variations, alterations, transformations, and modifications asfall within the scope of the appended claims.

What is claimed is:
 1. A method of fabricating a transistor, comprising: providing a semiconductor substrate having a surface; forming a nitride layer outwardly of the surface of the substrate; oxidizing the nitride layer to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer; depositing a high-K layer outwardly of the nitride layer; forming a conductive layer outwardly of the high-K layer; patterning and etching the conductive layer, the high-K layer, and the nitrided silicon oxide layer to form a gate stack; forming sidewall spacers outwardly of the semiconductor substrate adjacent to the gate stack; and forming source/drain regions in the semiconductor substrate adjacent to the sidewall spacers.
 2. The method of claim 1, wherein forming the nitride layer comprises subjecting the surface of the substrate to plasma nitridation.
 3. The method of claim 1, wherein the thickness of the nitrided Silicon oxide layer is less than about 20 Angstroms.
 4. The method of claim 1, wherein the high-K dielectric layer comprises an oxygen-containing material.
 5. The method of claim 1, wherein the high-K dielectric layer comprises a material selected from the group consisting of Ta₂O₅, BaTiO₃, TiO₂, CeO₂, and barium strontium titanate.
 6. The method of claim 2, wherein the plasma nitridation comprises high density plasma nitridation.
 7. The method of claim 2, wherein the plasma nitridation uses a nitrogen-containing precursor selected from the group consisting of N₂ or NH₃ or a mixture thereof with an inert gas.
 8. The method of claim 1, wherein the oxidizing occurs at a temperature in the range of 600 to 1000° C.
 9. The method of claim 1, further comprising removing an oxide layer from the surface of the substrate before forming the nitride layer outwardly of the surface of the substrate.
 10. A method of fabricating a transistor, comprising: providing a semiconductor substrate having a surface; forming a nitride layer outwardly of the surface of the substrate; oxidizing the nitride layer to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer, wherein the thickness of the nitrided silicon oxide layer is less than about 20 Angstroms; forming a conductive layer outwardly of the nitrided silicon oxide layer; patterning and etching the conductive layer and the nitrided silicon oxide layer to form a gate stack; forming sidewall spacers outwardly of the semiconductor substrate adjacent to the gate stack; and forming source/drain regions in the semiconductor substrate adjacent to the sidewall spacers.
 11. The method of claim 10, wherein forming the nitride layer comprises subjecting the surface of the substrate to plasma nitridation.
 12. The method of claim 11, wherein said plasma nitridation comprises high density plasma nitridation.
 13. The method of claim 11, wherein the plasma nitridation uses a nitrogen-containing precursor selected from the group consisting of N₂ or NH₃ or a mixture thereof with an inert gas.
 14. The method of claim 10, further comprising removing an oxide layer from the surface of the substrate before forming the nitride layer outwardly of the surface of the substrate.
 15. The method of claim 14, wherein removing an oxide layer from the surface of the substrate comprises stripping the surface of the substrate with hydrofluoric acid.
 16. A semiconductor structure, comprising: a semiconductor substrate having a surface; a gate stack outward of the surface of the semiconductor substrate, the gate stack comprising: a nitrided silicon oxide layer comprising an oxide layer beneath a nitride layer; a high-K dielectric layer outward of the nitrided silicon oxide layer; and a conductive layer outward of the high-K layer; sidewall spacers outward of the semiconductor substrate adjacent to the gate stack; and source/drain regions in the semiconductor substrate adjacent to the sidewall spacers.
 17. The semiconductor structure of claim 16, wherein: the nitride layer has a maximum atomic percentage of nitrogen of between 10 and 20 percent; and the oxide layer has a maximum atomic percentage of nitrogen of between 8 and 14 percent.
 18. The semiconductor structure of claim 16, wherein a thickness of the nitrided silicon oxide layer is less than about 20 Angstroms.
 19. The semiconductor structure of claim 16, wherein the high-K dielectric layer comprises an oxygen-containing material.
 20. The semiconductor structure of claim 16, wherein the high-K dielectric layer comprises a material selected from the group consisting of Ta₂O₅, BaTiO₃, TiO₂, CeO₂, and barium strontium titanate. 